1. Field of the Invention
The invention relates generally to conversion of a digital voltage signal into an analog current signal. The invention relates more specifically to an interface portion of a local area network (LAN) in which a current signal is to be generated in response to a digital voltage signal while satisfying prespecified current magnitude constraints and prespecified frequency constraints.
2. Description of the Related Art
Local area networks (LAN's) and wide area networks (WAN's) are becoming increasingly popular as a means for transferring data between spaced-apart data terminal equipment units (DTE's).
Standardized electrical interface requirements have to be complied with at points where different pieces of equipment (including those from different manufacturers) couple to a particular network. Conformity is necessary if signals output by one piece of equipment are to be appropriately received and understood by other pieces of equipment. Communication standards often specify certain voltage ranges and/or current ranges and/or impedance values which are to be maintained at each interface point. Waveshapes and timings are also commonly specified.
IEEE Standard 802.3 is representative of the type of interface standards found in commercial use. It defines a carrier sense multiple access with collision detection method. Ethernet is a popular LAN architecture which conforms to the IEEE 802.3 standard. An Ethernet network comprises a communications medium including a pair of wires (e.g., in twisted pair configuration or in a coaxial cable configuration) extending through a plurality of communication interface nodes.
Each Ethernet interface node includes a medium attachment unit (MAU) coupled directly to the two wires of the communication cable and an attachment unit interface (AUI) coupling the medium attachment unit (MAU) to local data terminal equipment (DTE).
A voltage-to-current, digital-to-analog waveform-shaping unit (hereafter, V/I:D/A unit) is provided within the medium attachment unit (MAU) at the point where the MAU connects to the communication cable. The V/I:D/A unit is supposed to receive a high-frequency digital voltage signal and in response, output a corresponding high-frequency analog current signal. The output current signal is then injected into the communication cable.
IEEE Standard 802.3 imposes a number of constraints on the current signal output by the V/I:D/A unit. The average DC magnitude of the output current must be in the range -37 milliamperes (mA) to -45 mA. The AC component of the output current must have at least a peak value of 28 mA, but the peak output current is not permitted to become positive. Additionally, the 10%-90% rise/fall time of the output current signal is specified as 25 .+-.5 nS (nanoseconds) when the data rate is 10Mb/s (megabits per second). Moreover, second and third harmonic components of the output current must be at least 20 dB below the fundamental component, fourth and fifth harmonics must be at least 30 dB below fundamental, sixth and seventh harmonics must be at least 40 dB below fundamental and all higher harmonics must be at least 50 dB below fundamental.
The IEEE 802.3 Standard specification suggests a frusto-triangular waveform for the output current. The suggested waveform peaks just below 0 mA, has an average value at -41 mA and a minimum value at -90 mA. (See FIG. 1C.)
Meeting the above IEEE 802.3 requirements and suggestions has proven difficult, particularly in cases where the V/I:D/A unit is to be mass produced.
One proposed design for a V/I:D/A unit comprises a plurality of series connected stages consisting in the recited order of: (1) a reference current source for generating a DC reference current, (2) a modulator for modulating the reference current with an externally supplied high-frequency, input voltage signal, (3) a current-to-voltage (I/V) converter for converting the modulated reference current into a modulated reference voltage, (4) a voltage-driven active filter for filtering the output voltage signal of the I/V converter, (5) a voltage-to-current (V/I) converter for converting a voltage output of the filter back into a current, and (6) a current multiplier for multiplying the magnitude of the current output by the V/I converter. (A block diagram of this proposed structure is shown in FIG. 1A.)
The proposed structure suffers from a number of drawbacks. Conventional active filters, such as that used in the fourth stage, inherently add an offset error to the signal that is being filtered. To maintain precision, in subsequent stages, a compensating offset is provided in the subsequent V/I converter (fifth stage) to assure that the final output current (I.sub.OUT) complies with minimum, maximum and average current levels specified by IEEE 802.3.
Offset compensation in the V/I converter (fifth stage), however, distorts the frequency response of the overall V/I:D/A unit. The design of the active filter (fourth stage) needs to be adjusted to counteract the distortion. Precise adjustment is difficult to achieve in mass-production environments.
The offset compensation in the V/I converter (fifth stage) also adds delay into the series path through which the high-frequency input voltage signal travels. This affects the frequency and rise/fall time characteristics of the output current signal in a detrimental way.
The input source impedance of the conventional, voltage-driven active filter poses yet another design problem. The input source impedance shifts the location of design-specified poles and zeroes of the filter, making it difficult to precisely set them at desired points in the real/imaginary plane until the input source impedance is first specified.
In summary, it is difficult to mass produce systems which consistently meet IEEE 802.3 specifications by using the conventional offset-compensating design and the conventional voltage-driven active filter design.